REPARA

Introduction

In recent years, traditional processors have not been able to translate the advances of silicon fabrication technology into corresponding performance gains. This has been due to weaknesses inherent in the current sequential programming model, which has not changed significantly since the late 1940’s, as well as due to physical constraints, such as practical limits on the energy consumption and the associated cooling efforts for a processor. To keep satisfying the ever-growing demand for computing power, these difficulties have forced a shift from homogeneous machines relying on a one single kind of fast processing element (the CPU) such as typical PCs some years ago, programmed mostly sequentially, to heterogeneous architectures combining different kinds of processors (such as CPUs, GPUs and DSPs) each specialized for certain tasks (as PCs nowadays), and programmed in a highly parallel fashion yet poorly optimising the available resources towards performance and low energy consumption.

Goal

The REPARA project aims to help the transformation and deployment of new and legacy applications in parallel heterogeneous computing architectures while maintaining a balance between application performance, energy efficiency and source code maintainability.

Objectives

  • O1: Language representation.
  • O2: Application partitioning.
  • O3: Source code transformation.
  • O4: Compilation into reconfigurable hardware.
  • O5: Software quality modelling.
  • O6: Runtime engines.
  • O7: Framework validation.

Project Funding

  • This project is co-funded by the Seventh Framework Programme (FP7).
  • Total cost: 3,682,223 €.
  • Funding: 2,671,000 €.
  • Start date: 1 September 2013.
  • Duration: 36 months.

FP7