D4.4: Source code transformations for fine grained parallelism

This document describes deliverable D4.4. Source code transformations for fine grained parallelism, which is part of task T4.3. The deliverable’s results specify the transformation of annotated REPARA C++ code to FastFlow pipeline and DSP/FPGA source code. Those transformations are realized as Continue reading D4.4: Source code transformations for fine grained parallelism

D5.3: Optimized multi-threaded mapping to reconfigurable hardware

The ThreadPoolComposer (TPC) tool has been refined to support the automated insertion of custom-generated (non-Vivado HLS) IP cores into the thread-pool of hardware processing elements. This not only allows the use of highly optimized cores formulated in traditional hardware design Continue reading D5.3: Optimized multi-threaded mapping to reconfigurable hardware

D2.5: Semantic specication for libraries

This document describes the deliverable D2.5 named Semantic specication for libraries. In document we present dierent mechanisms for specifying the semantic properties of libraries in generic terms. We explore two dierent alternative specications: axiom based and compiletime contracts. First mechanism Continue reading D2.5: Semantic specication for libraries

D6.3: Dynamic runtimes with auto-tuning capabilities

The REPARA Project aims to deploy software kernels of a sequential application written in C++ in a parallel heterogeneous platform by using static or dynamic scheduling and mapping techniques with the objective to improve both the performance and the energy Continue reading D6.3: Dynamic runtimes with auto-tuning capabilities

D5.4: Reconfigurable hardware integration into runtime engines

The REPARA Project aims to provide a uniform programming interface for applications on parallel heterogeneous platforms to improve both the performance, as well as the energy efficiency. Field-programmable gate arrays (FPGAs) are characterized by their potential for deep spatial parallelism Continue reading D5.4: Reconfigurable hardware integration into runtime engines