D5.2: Target platform for stand-alone hw execution and library of optimized module

The Repara Project targets the utilization of parallel heterogeneous hardware platforms such as GPGPUs, DSPs or FPGAs within a common design flow. Enhancements in terms of energy efficiency as well as performance shall be achieved by executing individual parts of Continue reading D5.2: Target platform for stand-alone hw execution and library of optimized module

D6.2: Dynamic runtimes for heterogeneous platforms

The REPARA Project aims to deploy software kernels of a sequential application written in C++ in parallel heterogeneous platforms by using static or dynamic scheduling and mapping techniques in order to improve both the performance and the energy efficiency. The Continue reading D6.2: Dynamic runtimes for heterogeneous platforms

D7.2: Detailed quantitative performance and energy models

In this document, we describe a method for deriving detailed quantitative models for predicting performance, power, and energy consumption based on source code software metrics, with a special focus on recongurable hardware. The models are built by employing various statistical and Continue reading D7.2: Detailed quantitative performance and energy models

D6.1: Static run times for coordination in heterogeneous platforms

This report is introduces static run-times for coordination in heterogeneous platforms, which is a prototype deliverable. It describes the basic run-time engine supporting statically partitioned applications. FastFlow is an open-source, structured parallel programming framework written in C/C++ originally conceived to support highly efficient stream Continue reading D6.1: Static run times for coordination in heterogeneous platforms

D5.1: Compile flow for behavioral transformation to reconfigurable hardware

This report introduces the compile flow for behavioral transformation to reconfigurable hardware. It describes the automated compilation flow of isolated C/C++ kernels to hardware thread-pools and their integration into higher-level run-times on the software-side. In the context of the REPARA project, this prototype Continue reading D5.1: Compile flow for behavioral transformation to reconfigurable hardware