D5.3: Optimized multi-threaded mapping to reconfigurable hardware

The ThreadPoolComposer (TPC) tool has been refined to support the automated insertion of custom-generated (non-Vivado HLS) IP cores into the thread-pool of hardware processing elements. This not only allows the use of highly optimized cores formulated in traditional hardware design Continue reading D5.3: Optimized multi-threaded mapping to reconfigurable hardware

D5.4: Reconfigurable hardware integration into runtime engines

The REPARA Project aims to provide a uniform programming interface for applications on parallel heterogeneous platforms to improve both the performance, as well as the energy efficiency. Field-programmable gate arrays (FPGAs) are characterized by their potential for deep spatial parallelism Continue reading D5.4: Reconfigurable hardware integration into runtime engines

D5.2: Target platform for stand-alone hw execution and library of optimized module

The Repara Project targets the utilization of parallel heterogeneous hardware platforms such as GPGPUs, DSPs or FPGAs within a common design flow. Enhancements in terms of energy efficiency as well as performance shall be achieved by executing individual parts of Continue reading D5.2: Target platform for stand-alone hw execution and library of optimized module

D5.1: Compile flow for behavioral transformation to reconfigurable hardware

This report introduces the compile flow for behavioral transformation to reconfigurable hardware. It describes the automated compilation flow of isolated C/C++ kernels to hardware thread-pools and their integration into higher-level run-times on the software-side. In the context of the REPARA project, this prototype Continue reading D5.1: Compile flow for behavioral transformation to reconfigurable hardware