The Repara Project targets the utilization of parallel heterogeneous hardware platforms such as GPGPUs, DSPs or FPGAs within a common design flow. Enhancements in terms of energy efficiency as well as performance shall be achieved by executing individual parts of a program on the best suited platform. FPGA programming offers high degrees of freedom as the complete hardware design can be tailored to desired functionality, while featuring a low energy footprint in comparison to different accelerators (GPGPUs, ..). However, FPGA platforms lack of basic operations to interact with the accelerator, e.g., data transfers or function callbacks. This document presents the key components of the proposed hardware architecture for on-chip memory interfaces, efficient data transfer mechanisms and hardware kernel communication/signalling primitives and demonstrates its usage by employing a complete FPGA hardware design.