D5.4: Reconfigurable hardware integration into runtime engines

The REPARA Project aims to provide a uniform programming interface for applications on parallel heterogeneous platforms to improve both the performance, as well as the energy efficiency. Field-programmable gate arrays (FPGAs) are characterized by their potential for deep spatial parallelism and good energy-efficiency, but require a high level of hardware design and electronics expertise for their programming. This document describes the efforts undertaken in Work Package WP5 to specify a uniform programming interface that can be used by high-level, parallel heterogeneous runtimes to offload computation to FPGA accelerators. In particular, we discuss the C/C++ Application Programming Interfaces (API) TPC API and TPC++ API we developed and implemented in Task 5.4, and detail some of the work that was required at lower levels on the actual hardware in the first half of this document. The second half contains a description of a prototype of the FastFlow runtime with FPGA support, which describes in more detail how a higher-level runtime utilizes the programming interfaces discussed in the first half of the document and demonstrates parallel programming for FPGAs with FastFlow. Both APIs (TPC API and TPC++ API) and the FastFlow runtime engine will be released under a liberal free software license (LGPLv3 [1]) which facilitates both academic and commercial use, as well as third-party implementations of additional platforms (i.e., new boards / devices). The latter is of particular interest regarding exploitation, since the APIs are highly
versatile and can be applied to accelerator devices in general. This has already been demonstrated in REPARA by the integration of Digital Signal Processors (DSP), an entirely different class of devices, under the TPC API. Furthermore, enabling new accelerators for use under TPC API is significantly easier than integrating them in OpenCL [2] or HSA [3] environments.

ICT-609666-D5.4

 

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